The field of the invention relates generally to a method for fabricating a semiconductor on insulator composite substrate, such as silicon-on-sapphire (SOS). More particularly, the field of the invention relates to a method for making a resistor, transistor, or memory cell utilizing an ultra thin silicon layer on a sapphire structure and for providing a resistive load which is self-aligned to a corresponding transistor, thereby eliminating a polysilicon layer and providing an extremely compact memory cell or analog circuit.
Generally, a field effect transistor (FET) controls current conduction from a source region to a drain region by application of voltage to a gate conductor. If the gate conductor is insulated from the source-drain conduction channel, the device is called an insulated gate FET. The most common gate structure is that of metal oxide semiconductor, or the MOSFET. A variety of requirements force designs which contain doped semiconductor material below the insulating gate structure, i.e., in the conduction channel. As device dimensions shrink, doping concentrations must be increased to scale the depletion layer widths and thereby maintain proper transistor operation.
Dopant atoms and electrically active states (hereinafter called "fixed charge") in the conduction channel region of MOSFETs are charged and discharged during operation of the device. Since fixed charge is immobile, it does not contribute to FET current conduction. However, the charging and discharging of fixed charges introduces parasitic charge in the transistor. Parasitic charge results from excess dopant atoms and electrically active states. Parasitic charge has many negative effects, including scattering of conduction carriers; variation in threshold voltage; introduction of buried channel operation; introduction of a body effect; complication of device modeling; increased complexity for device and process design; increased electric fields; and difficulty in scaling devices to smaller dimensions or voltages, among others.
Dopant atoms are introduced into MOSFETs for specific reasons such as to adjust threshold voltage or to control substrate currents, with the aforementioned adverse side effects accepted as necessary by-products of dopant atom introduction. It would be very desirable to be able to introduce only the specific type, quantity and location of dopant atoms which are necessary to achieve the desired electrical characteristics for the device, and to avoid or eliminate all other dopant atoms and their parasitic effects. The "ideal" semiconductor material would thus include a completely monocrystalline, defect-free silicon layer of sufficient thickness to accommodate the fabrication of active devices thereon. Ideal operation of MOSFETs would occur if there were no parasitic charge in the conduction channel.
Another requirement for MOSFETs is to set threshold voltage, which is the gate voltage necessary to initiate conduction. A common technique for setting threshold voltage is to modify the dopant concentrations in the channel region. However, this approach has the undesirable side effects associated with dopant charge mentioned above. Also, adjusting threshold voltage by ion implantation requires at least two and often four masking steps which increase cost and decrease yield.
A memory cell for a typical computer or microprocessor commonly stores bits of data as a charge on a floating gate. A nonvolatile or static random access memory (SRAM) typically stores data as a charge on the gate of a field effect transistor or as the presence or absence of charge on a plurality of cross-coupled pairs of field effect transistors. A bit logic state written in a static RAM (SRAM) remains in that same logic state until rewritten to another bit logic state, or until power is turned off. Also, because SRAMs are made from cross coupled active devices, SRAMs are the fastest type of memory. In a dynamic RAM data will disappear, typically, in less than a second unless constantly refreshed. For these reasons, SRAMs often are desirable as memory elements because they are fast, do not need refresh clocks, or involve other timing complexities which compete with normal memory access cycles and must be properly synchronized. Thus, for certain systems the SRAM predominates as the memory cell of choice due to its speed and simplicity.
As is well recognized in the art, it is frequently desirable to build SRAMs using field effect transistors (FETs) and, in particular, metallic oxide semiconductor field effect transistors (MOSFETs). Cells in conventional SRAMs have used FETs in primarily two configurations: a four MOSFET transistor configuration and a six MOSFET transistor configuration. SRAMs with four transistors in a cell are typically referred to as 4 T SRAMs, and SRAMs with six transistors in a cell are typically referred to as 6 T SRAMs.
Conventional 4 T and 6 T SRAMs present problems when fabricated using conventional semiconductor processing techniques. In addition to four transistors, each cell of a 4 T SRAM typically requires two resistors. The resistors are formed in a well-known manner to provide a resistance load for a typical MOSFET. To function properly, that is, to enable each memory cell to properly represent logic states, these resistors must be made of a high resistivity material. The resistors enable the MOSFET to perform logic switching. That is, the resistors enable the MOSFET to open and close to generate full swings between the power supply voltages. The switching between the power supply voltages represents the two logic states HIGH and LOW. The resistors thereby prevent inadvertent switching at insignificant power levels in a well-known manner. The resistors must be made from high resistivity material. This material does not exist in the remainder of the process. To use conventional processing techniques to manufacture active transistors together with high resistance loads on a single semiconductor wafer, an additional layer of material, such as polysilicon, often must be used. This adds complexity and cost to the basic CMOS process. Alternatively, if a high resistance layer were made in the substrate, unacceptable parasitic effects would result and the layout area would be unacceptably large. The resistors are constructed in the second layer of polysilicon in a well-known manner.
Creating this additional layer of material on the semiconductor wafer increases the number and complexity of processing steps required to manufacture an SRAM. These steps can be critical, time consuming and can present significant obstacles in fabricating an SRAM. For example, because of the extra polysilicon layer, the process may have to align separate layers and conductively connect the layers through contact holes or vias. The second layer may have to be connected with a supply voltage in a conventional manner. The steps disadvantageously may require precise lithography tolerances, for example, in order to align the layers. In addition to increasing cost and processing complexity, such steps may dramatically decrease process yield.
Adding layers to a device complicates the lithography process. In particular, each layer of material increases the maximum step height of the device. This can have the disadvantage of causing a depth of focus problem in the lithography process. To increase the depth of focus of the lithography process. expensive and complex equipment may be necessary, which substantially increases fabrication cost per chip. As a result, it is often desirable to eliminate additional layers in order to simplify the lithography process.
Also, it can be difficult to precisely control deposition of polysilicon in MOS processing with the requisite uniformity and conduction characteristics. Polycrystalline silicon (polysilicon) is composed of many small (sub-micrometer size) crystals with generally random orientation. In order to fabricate a useful semiconductor device, it typically is necessary to implant or diffuse dopant atoms into the polysilicon substrate. Conventional methods of ion implantation and subsequent annealing cause polycrystalline crystals to expand thereby reducing the polysilicon's resistivity and compromising its performance as an SRAM resistor. This obstacle can constrain the initial polysilicon deposition and subsequent processing temperature and times of the SRAM.
A six transistor (6 T) SRAM, typically includes four NMOS transistors and two PMOS transistors. In these 6 T SRAMs, the two PMOS transistors replace the high resistance resistors used in the 4 T SRAMs. In a typical 6 T SRAM, the complimentary n and p channel transistors are adjacent. Accordingly, an additional layer of material (like that used to form the 4 T SRAM resistors) ordinarily is not required. As a result, the 6 T SRAM fabrication process can eliminate some of the processing steps used to fabricate a 4 T SRAM. The 6 T SRAM technology also can reduce (by as much as a factor of 1000) the high leakage currents that are commonly found in 4 T SRAMs. This is due to the off current of a PMOS device being typically 10.sup.-12 Amps, whereas the resistors typically draw 10.sup.-8 to 10.sup.-9 Amps.
The fabrication of a 6 T SRAM, however, can present other problems. Because a transistor is more complex than a resistor, it requires more die area. Transistors typically have a larger critical area than the resistors. That is, they present a much larger area for possible defects. This large critical area can reduce manufacturing yield. Because 6 T SRAM technology replaces the resistors of the 4 T SRAMs with transistors, a memory cell comprising 6 T SRAMs typically has a larger critical area than a 4 T SRAM cell. Thus, there is a critical need to eliminate defects such as particles, dislocations or the like, which may give rise to leakage current and the formation of parasitic charge. This in turn may facilitate the formation of parasitic bipolar transistor action due to adjacent regions of n and p type material in a transistor of an SRAM memory cell.
Additionally, during the operation of either a 4 T or 6 T SRAM, a latch-up condition may occur between adjacent n and p channel transistors. This latch-up condition occurs because the substrate typically used in an SRAM does not fully insulate the different regions of the device. As is well known in the art, a "latch-up" conduction occurs when unwanted or parasitic npn and pnp bipolar transistor action causes a low resistance path between the power supply and ground. As a result, n and p channel transistors must be spaced apart whether they are used in an SRAM control circuitry, or in the core of an SRAM itself. Consequently, the need to isolate adjacent n and p channel transistors used in SRAMs can consume even more cell or die space. Since for a given defect density, large die area results in low yield, the end result can be a low yield, large die and highly expensive SRAM.
Previously, silicon-on-sapphire (SOS) has been used for high performance MOSFET microelectronics, primarily for applications requiring radiation immunity. Typically, a silicon film is epitaxially grown on a sapphire substrate. Ideally, the silicon film is thin compared to the source to drain separation (called the channel length) and the insulating substrate is thick enough to ensure no significant electrostatic coupling to a back plane. Due to crystal and thermal expansion mismatches between the silicon and the sapphire, the silicon films are typically heavily populated with crystalline defects and electrically active states. The dominant type of crystalline defects are commonly called "twins". The quality of the silicon films can be improved by increasing the thickness of the silicon, hence traditional SOS is made with silicon films between 400 and 800 nanometers thick. This film thickness is capable of supporting transistors with channel lengths down to about 1 micron. Submicron channel length devices cannot be made in traditional SOS materials as thinner films are required.
The advantages of utilizing a composite substrate comprised of a monocrystalline semiconductor layer, such as silicon, epitaxially deposited on a supporting insulative substrate are well recognized. These advantages include the substantial reduction of parasitic capacitance between charged active regions and the substrate and the effective elimination of leakage currents flowing between adjacent active devices. This is accomplished by employing as the substrate an insulative material, such as sapphire (Al.sub.2 O.sub.3) and providing that the conduction path of any interdevice leakage current must pass through the substrate.
An "ideal" silicon-on-sapphire wafer may be defined to include a completely monocrystalline, defect-free silicon layer of sufficient thickness to accommodate the fabrication of active devices therein. The silicon layer would be adjacent to a sapphire substrate and would have a minimum of crystal lattice discontinuities at the silicon-sapphire interface. Previous attempts to fabricate this "ideal" silicon-on-sapphire (SOS) wafer have been frustrated by a number of significant problems.
A first significant problem encountered in attempts to fabricate the ideal SOS wafer is the substantial incursion of contaminants into the epitaxially deposited silicon layer. In particular, substantial concentrations of aluminum contaminants, diffused from the sapphire substrate, are found throughout the silicon epitaxial layer. The inherent consequence of a high concentration of aluminum contaminants, effectively acting as acceptor-type impurities in the silicon epitaxial layer, is that there are unacceptably high leakage currents between the source and drain regions of p-channel active devices, such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) and MOSFETs (Metal Semiconductor FET). These leakage currents may be of sufficient magnitude that the p-channel active devices may be considered to be always in an "on", or conducting state.
The incursion of substrate-oriented contaminants into the silicon layer was found to be an inherent consequence of high temperature processing steps. Such steps are typically utilized in both the initial epitaxial deposition of the silicon layer and the subsequent annealing of the silicon layer to reduce crystalline defects contained therein. Thus, it was recognized that high temperature annealing needed to be avoided to prevent the substantial incursion of substrate-orientated contaminants into the silicon layer.
However, in the absence of a high temperature anneal, a second problem appears. The crystalline quality of the silicon layer, as epitaxially deposited, is of insufficient quality to permit the fabrication of active devices therein. It was discovered that the dominant crystal defects, i.e., twins, could be eliminated by solid phase epitaxial (SPE) regrowth, a process described in U.S. Pat. No. 4,177,084, entitled "METHOD FOR PRODUCING A LOW DEFECT LAYER OF SILICON-ON-SAPPHIRE WATER", issued to Lau et al. As described by Lau et al., the SPE process provides a low temperature subprocess for improving the crystallinity of the silicon epitaxial layer of a silicon-on-sapphire composite substrate. The SPE process involves the high energy implantation (typically at 40 KeV to 550 KeV) of an ion species, such as silicon, into the silicon epitaxial layer at a sufficient dose (typically 10.sup.15 to 10.sup.16 ions/cm.sup.2) to create a substantially amorphous silicon layer lying adjacent the silicon/sapphire interface while leaving a substantially crystalline layer at the surface of the original epitaxial layer. The thickness of the silicon epitaxial layer is substantially that intended for the completed silicon-on-sapphire composite substrate (typically 3000A-6000A). The ion species is implanted through the majority of the epitaxial layer so that the maximum disruption of the silicon crystal lattice is near, but not across, the silicon/sapphire interface to ensure that the amorphous region is adjacent the sapphire substrate. Throughout the ion implantation, the sapphire substrate is kept below about 100.degree. C. by cooling with Freon or liquid Nitrogen. A single step low temperature (600.degree. C.) annealing of the composite substrate is then performed to convert the amorphous silicon layer into crystalline silicon. During this regrowth, the remaining crystalline surface portion of the silicon layer effectively acts as a nucleation seed so that the regrown portion of the silicon epitaxial layer has a common crystallographic orientation and is substantially free of crystalline defects.
While Lau's SPE process does significantly improve the crystallinity of the silicon epitaxial layer, it also facilitates the diffusion of aluminum from the sapphire substrate (Al.sub.2 O.sub.3) into the silicon epitaxial layer, which dopes the silicon film p-type. The contaminant concentration resulting from the use of the SPE process is, unfortunately, sufficient to preclude the practical use of integrated circuits fabricated on composite substrates, such as silicon on sapphire, processed with this SPE subprocess. The reasons for the failure of active devices to operate correctly are essentially the same as given above with regard to composite substrates fabricated utilizing high temperature processing steps. Additionally, it has been observed that the method described by Lau et al., can leave enough electrically active states in the silicon epitaxial layer to preclude its use for fabrication of integrated circuits using silicon on sapphire.
U.S. Pat. No. 4,509,990, entitled "SOLID PHASE EPITAXY AND REGROWTH PROCESS WITH CONTROLLED DEFECT DENSITY PROFILING FOR HETEROEPITAXLIAL SEMICONDUCTOR ON INSULATOR COMPOSITE SUBSTRATES", issued to Vasudev, also describes use of ion implantation and solid phase regrowth to prepare a silicon-on-sapphire wafer. In a first principle embodiment, a method for fabricating a silicon-on-sapphire wafer very similar to that taught by Lau et al. is described with the additional requirement that the implantation energy and the ion dose are constrained such that they are sufficiently low so as not to exceed the damage density threshold of the sapphire substrate. In a second principle embodiment, the method describes a residual high defect density in the silicon layer near the sapphire substrate. Both embodiments utilize a method for controlling the temperature of the rear surface of the sapphire substrate by mounting the substrate on a heat sink with either a thin film of thermal paste or a thin film of silicon positioned intermediate to the rear surface of the substrate and the heat sink to provide a high heat conductivity interface therebetween. During the ion implantation, the temperature of the heat sink is held at a constant temperature (typically between -20.degree. C. and 250.degree. C.) resulting in a substantial thermal gradient between the rear surface of the sapphire and the silicon layer (typically 150.degree. C. to 200.degree. C.). Thus, it follows that the silicon layer is at a temperature falling in the range of 130.degree. C. to 450.degree. C.
It has been found that the process described by Vasudev can result in incomplete and non-uniform removal of crystalline defects and electrically active states from the silicon layer due to non-uniform thermal contact of the rear surface of the sapphire with the heat sink. When the thermal paste is used, any air bubbles in the paste interface can result in the nonuniform control of the silicon layer temperature. Additionally, further processing of the wafer is made more difficult because it is necessary to completely remove all residues of the thermal paste before proceeding. While coating the rear surface of the sapphire with silicon to provide a thermal interface removes the problem of cleaning paste from the wafer before further processing, it has also been found to provide non-uniform temperature control of the silicon layer, due to roughness of the rear surface of the sapphire. Even when great care is taken to smooth the rear surface of the sapphire prior to applying the silicon interface layer, a costly and time consuming process, warping of the substrate caused by heating and cooling of the sapphire during the implantation can result in non-uniform thermal contact between the rear surface of the sapphire and the heat sink.
U.S. Pat. No. 4,659,392, entitled "SELECTIVE AREA DOUBLE EPITAXIAL PROCESS FOR FABRICATING SILICON-ON-INSULATOR STRUCTURES FOR USE WITH MOS DEVICES AND INTEGRATED CIRCUITS", issued to Vasudev, describes another method for tailoring defect densities in regions of silicon on insulator wafers. Using this process, the defect structure and dopant concentrations near the interface between the silicon and the insulator are optimized for specific applications. However, such residual defects would make such silicon films inappropriate for construction of fully depleted transistors.
Other methods to prepare silicon on sapphire films have been described. U.S. Pat. No. 4,385,937, entitled "REGROWING SELECTIVELY FORMED ION AMORPHOSIZED REGIONS BY THERMAL GRADIENT", issued to Ohmura, describes a method which uses large thermal gradients during solid phase regrowth to enhance electron mobility in the silicon semiconductor layer. U.S. Pat. No. 4,775,641, entitled "METHOD OF MAKING SILICON-ON-SAPPHIRE SEMICONDUCTOR DEVICES", issued to Duffy et al., describes a method which intentionally forms a silicon layer adjacent an insulating substrate which has a high density of naturally occurring crystallographic defects. The purpose of this region is to substantially reduce the back-channel leakage that occurs when the device is operated after being irradiated. U.S. Pat. No. 4,588,447, entitled "METHOD OF ELIMINATING P-TYPE ELECTRICAL ACTIVITY AND INCREASING CHANNEL MOBILITY OF SI-IMPLANTED AND RECRYSTALLIZED SOS FILMS", issued to Golecki, describes use of ion implantation, recrystallization and oxygen diffusion to neutralize aluminum in the silicon film. The resulting oxide layer on the outward surface is subsequently densified and etched away. U.S. Pat. No. 4,523,963, entitled "METHOD OF FABRICATING MOS DEVICE ON A SOS WAFER BY STABILIZING INTERFACE REGION WITH SILICON AND OXYGEN IMPLANT", issued to Ohta, et al. describes use of implanting both silicon and oxygen to form recrystallized silicon films. An insulating layer is intentionally formed at the interface of the sapphire substrate. This insulating layer contains a high density of crystalline defects and dopants.
The paper entitled "THIN (100 nm) SOS FOR APPLICATION TO BEYOND VLSI MICROELECTRONICS", published in the Mat. Res. Soc. Symp. Proc. Vol. 107, pp. 365-376, 1988, authored by Reedy et al. discusses preparation techniques for SOS films using a double anneal with temperatures as high as 1050.degree. C. Mention is made that adequate thermal contact must be made to prevent self annealing, however, no method of providing such contact is disclosed. Characteristics of bulk silicon and the SOS films thus produced are compared. Likewise, it is noted that n and p channel transistors which were fabricated in these SOS films exhibited performance characteristics which rivaled those of similar devices fabricated in bulk silicon. However, there is no discussion of fully depleted transistor operation in this paper.
The paper entitled "HIGH-QUALITY CMOS IN THIN (100 nm) SILICON ON SAPPHIRE", published in IEEE Electron Device Letters, Vol. 9, No. 1, pp. 32-34, January, 1988, authored by Garcia et al., presents substantially the same information as the above referenced Reedy et al. paper with more emphasis placed on the characteristics of the enhancement-mode n and p channel MOSFET's fabricated in the SOS material.
Significant progress has been made in producing SOS material having low concentrations of crystalline defects and substrate contaminants in the silicon. However, none of the conventional work in this field appears to recognize or address the effects or origin of charge states, which may also be present. Additionally, there are no known teachings on how to produce SOS materials and to fabricate devices therein which do not have the undesirable charge states discussed above.
Therefore, there has been a need for an SRAM that achieves an area savings of 4 T SRAMs but with the simplified standard processing steps found in a 6 T SRAM. There also has been a need for an SRAM with increased reliability and immunity to latch-up. Unfortunately, conventional SOS and SOI techniques above have limited the fabrication of such devices, largely for the reasons set forth above.
Therefore, what is needed is a method for fabricating a thin layer of substantially pure silicon on a sapphire or other insulating substrate which layer is extremely uniform in thickness. The transistors and/or resistors of an SRAM could be manufactured in this layer eliminating some of the disadvantages of conventional SRAMs. Such a uniform layer, if fabricated on a sapphire substrate would advantageously have its conductivity controlled by normal ion implantation due to the uniform definition imposed by the sapphire substrate. Such a layer would initially have no dopant atoms or electrically active states. Substantially no electrically active states is defined as an areal density of electrically active states which is approximately 3.times.10.sup.11 cm.sup.-2 to 5.times.10.sup.11 cm.sup.-2.